⚡ 5-BIT TO MORSE CODE ENCODER CIRCUIT ⚡

Circuit Overview: This is a combinational logic circuit that takes a 5-bit binary input (b4 b3 b2 b1 b0) representing letters A-Z (0-25) and outputs the corresponding Morse code pattern using AND, OR, and NOT gates.

Block Diagram

b4 b3 b2 b1 b0 NOT GATES ¬ ¬b4 ¬ ¬b3 ¬ ¬b2 ¬ ¬b1 ¬ ¬b0 AND/OR GATE NETWORK & Letter A & Letter B & Letter Z ...26 decoders total... OUTPUT MUX Selects Morse code pattern MORSE OUTPUT ".-" or "-..." etc. LEGEND: Input Bits NOT Gates AND Gates Multiplexer

Boolean Expressions for Each Letter

Letter Binary (b4 b3 b2 b1 b0) Boolean Expression Morse
A 00000 ¬b4 · ¬b3 · ¬b2 · ¬b1 · ¬b0 .-
B 00001 ¬b4 · ¬b3 · ¬b2 · ¬b1 · b0 -...
C 00010 ¬b4 · ¬b3 · ¬b2 · b1 · ¬b0 -.-.
D 00011 ¬b4 · ¬b3 · ¬b2 · b1 · b0 -..
E 00100 ¬b4 · ¬b3 · b2 · ¬b1 · ¬b0 .
F 00101 ¬b4 · ¬b3 · b2 · ¬b1 · b0 ..-.
G 00110 ¬b4 · ¬b3 · b2 · b1 · ¬b0 --.
H 00111 ¬b4 · ¬b3 · b2 · b1 · b0 ....
I 01000 ¬b4 · b3 · ¬b2 · ¬b1 · ¬b0 ..
J 01001 ¬b4 · b3 · ¬b2 · ¬b1 · b0 .---
K 01010 ¬b4 · b3 · ¬b2 · b1 · ¬b0 -.-
L 01011 ¬b4 · b3 · ¬b2 · b1 · b0 .-..
M 01100 ¬b4 · b3 · b2 · ¬b1 · ¬b0 --
N 01101 ¬b4 · b3 · b2 · ¬b1 · b0 -.
O 01110 ¬b4 · b3 · b2 · b1 · ¬b0 ---
P 01111 ¬b4 · b3 · b2 · b1 · b0 .--.
Q 10000 b4 · ¬b3 · ¬b2 · ¬b1 · ¬b0 --.-
R 10001 b4 · ¬b3 · ¬b2 · ¬b1 · b0 .-.
S 10010 b4 · ¬b3 · ¬b2 · b1 · ¬b0 ...
T 10011 b4 · ¬b3 · ¬b2 · b1 · b0 -
U 10100 b4 · ¬b3 · b2 · ¬b1 · ¬b0 ..-
V 10101 b4 · ¬b3 · b2 · ¬b1 · b0 ...-
W 10110 b4 · ¬b3 · b2 · b1 · ¬b0 .--
X 10111 b4 · ¬b3 · b2 · b1 · b0 -..-
Y 11000 b4 · b3 · ¬b2 · ¬b1 · ¬b0 -.--
Z 11001 b4 · b3 · ¬b2 · ¬b1 · b0 --..

Sum-of-Products (SOP) Form

General Form:

MORSE_OUTPUT = (Expression_A) + (Expression_B) + ... + (Expression_Z)

Where each term is a product (AND) of literals, and the sum represents OR operation.

Example for Letter 'A':
Output_A = ¬b4 · ¬b3 · ¬b2 · ¬b1 · ¬b0

This means: A is selected when ALL five bits are 0 (binary 00000 = decimal 0)
Example for Letter 'Z':
Output_Z = b4 · b3 · ¬b2 · ¬b1 · b0

This means: Z is selected when bits match 11001 (decimal 25)

Gate Count Analysis

Component Count Description
NOT Gates 5 One for each input bit (¬b4, ¬b3, ¬b2, ¬b1, ¬b0)
5-input AND Gates 26 One per letter (A-Z), each checks unique 5-bit pattern
26-input OR Gate 1 Combines all letter outputs (in reality: multiplexer)
Total Gates 32 Minimal for full 5-bit decoder
⚡ Circuit Characteristics:
• Type: Combinational Logic (no memory/state)
• Inputs: 5 bits (b4, b3, b2, b1, b0)
• Outputs: Morse code string (variable length)
• Propagation Delay: ~3 gate delays (NOT → AND → OR)
• Power: Static (no switching unless input changes)
• Implementation: Can be realized with 7400-series ICs or FPGA